Questions & Answers of Combinational and Sequential Logic Circuits

Question No. 21

Consider the following circuit which uses a 2-to-1 multiplexer as shown in the figure below. The Boolean expression for output F in terms of A and B is 


Question No. 46

The current state QA QB of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is

Question No. 47

The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of Q2Q1Q0=000. This state Q2Q1Q0=000 will repeat after ________ number of cycles of the clock CLK.

Question No. 147

In the following sequential circuit, the initial state (before the first clock pulse ) of the circuit is Q1Q0= 00. The state (Q1Q0), immediately after the 333rd clock pulse is

Question No. 148

A Boolean funcation f(A, B, C, D) = Π(1, 5, 12, 15) is to be implemented using an 8×1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs S2S1S0 of the multiplexer respectively.

Which one of the following options gives the correct inputs to pins 0,1,2,3,4,5,6,7 in order?

Question No. 31

A cascade of three identical modulo-5 counters has an overall modulus of

Question No. 161

A JK flip flop can be implemented by T flip-flops. Identify the correct implementation.

Question No. 231

A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don’t care condition, and Q is the output representing the state.

The logic gate represented by the state diagram is

Question No. 259

Two monoshot multivibrators, one positive edge triggered (M1) and another negative edge triggered (M2), are connected as shown in figure

The monoshots M1 and M2 when triggered produce pulses of width T1 and T2 respectively, where T1>T2. The steady state output voltage vo of the circuit is

Question No. 261

A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is 0002. The output is pulled high. The output of the circuit follows the sequence

Question No. 19

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

Question No. 20

Consider the given circuit.

In this circuit, the race around

Question No. 30

The state transition diagram for the logic circuit shown is

Question No. 46

A two bit counter circuit is shown below

It the state QAQB of the counter at the clock time tn is "10" then the state QAQB of the counter at tn + 3 (after three clock cycles) will be