GATE Questions & Answers of Combinational and Sequential Logic Circuits

What is the Weightage of Combinational and Sequential Logic Circuits in GATE Exam?

Total 25 Questions have been asked from Combinational and Sequential Logic Circuits topic of Analog and Digital Electronics subject in previous GATE papers. Average marks 1.60.

In the logic circuit shown in the figure, $ Y $ is given by


Which one of the following statements is true about the digital circuit shown in the figure


Digital input signals $ A,B,C $ with $ A $ as the MSB and $ C $ as the LSB are used to realize the Boolean function $ f=m_0+m_2+m_3+m_5+m_7 $ where $ m_i $ denotes the $ i^{th} $ minterm. In addition, $ F $ has a don’t care for $ m_1 $. The simplified expression for $ F $ is given by

The Boolean expression AB+AC+BC simplifies to

The output expression for the Karnaugh map shown below is


The logical gate implemented using then circuit shown below where, $ V_1 $ and $ V_2 $ are inputs (with $ 0\;V $ as digital $ 0 $ and $ 5\;V $ as digital 1) and $ V_{OUT} $ is the output, is


For a 3-input logic circuit shown below, the output $ Z $ can be expressed as


For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions QAQBQC=Q’AQ’BQ’C=100.



The minimum number of clock cycles after which the output Z would again become zero is__________

Consider the following circuit which uses a 2-to-1 multiplexer as shown in the figure below. The Boolean expression for output F in terms of A and B is 


The current state QA QB of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is

The output expression for the Karnaugh map shown below is


The Boolean expression $\overline{\left(a+\overline b+c+\overline d\right)+\left(b+\overline c\right)}$ simplifies to

The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of Q2Q1Q0=000. This state Q2Q1Q0=000 will repeat after ________ number of cycles of the clock CLK.

fA, ,B, C, D=M0,1,3,4,5,7,9,11,12,13,14,15 is a maxterm representation of a Boolean function $f\left(A,\;,B,\;C,\;D\right)$ where $A$ is the MSB and $D$ is the LSB. The equivalent minimized representation of this function is

In the following sequential circuit, the initial state (before the first clock pulse ) of the circuit is Q1Q0= 00. The state (Q1Q0), immediately after the 333rd clock pulse is

A Boolean funcation $ f\left(A,\;B,\;C,\;D\right)= $ Π(1, 5, 12, 15) is to be implemented using an 8×1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs S2S1S0 of the multiplexer respectively.

Which one of the following options gives the correct inputs to pins 0,1,2,3,4,5,6,7 in order?

A cascade of three identical modulo-5 counters has an overall modulus of

A JK flip flop can be implemented by T flip-flops. Identify the correct implementation.

A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don’t care condition, and Q is the output representing the state.

The logic gate represented by the state diagram is

Two monoshot multivibrators, one positive edge triggered (M1) and another negative edge triggered (M2), are connected as shown in figure

The monoshots M1 and M2 when triggered produce pulses of width T1 and T2 respectively, where T1>T2. The steady state output voltage vo of the circuit is

A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is 0002. The output is pulled high. The output of the circuit follows the sequence

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

Consider the given circuit.

In this circuit, the race around

The state transition diagram for the logic circuit shown is

A two bit counter circuit is shown below

It the state QAQB of the counter at the clock time tn is "10" then the state QAQB of the counter at tn + 3 (after three clock cycles) will be