The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of ${\mathrm{Q}}_{2}{\mathrm{Q}}_{1}{\mathrm{Q}}_{0}=000$. This state ${\mathrm{Q}}_{2}{\mathrm{Q}}_{1}{\mathrm{Q}}_{0}=000$ will repeat after ________ number of cycles of the clock CLK.
In the following sequential circuit, the initial state (before the first clock pulse ) of the circuit is ${Q}_{1}{Q}_{0}$= 00. The state (${Q}_{1}{Q}_{0}$), immediately after the ${333}^{\mathrm{rd}}$ clock pulse is
A Boolean funcation f(A, B, C, D) = $\mathrm{\Pi}$(1, 5, 12, 15) is to be implemented using an 8$\times $1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs ${S}_{2}{S}_{1}{S}_{0}$ of the multiplexer respectively.
Which one of the following options gives the correct inputs to pins 0,1,2,3,4,5,6,7 in order?
A cascade of three identical modulo-5 counters has an overall modulus of
A JK flip flop can be implemented by T flip-flops. Identify the correct implementation.
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don’t care condition, and Q is the output representing the state.
The logic gate represented by the state diagram is
Two monoshot multivibrators, one positive edge triggered (M_{1}) and another negative edge triggered (M_{2}), are connected as shown in figure
The monoshots M_{1} and M_{2} when triggered produce pulses of width T_{1} and T_{2} respectively, where T_{1}>T_{2}. The steady state output voltage v_{o} of the circuit is
A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is 000_{2}. The output is pulled high. The output of the circuit follows the sequence
The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is
Consider the given circuit.
In this circuit, the race around
The state transition diagram for the logic circuit shown is
A two bit counter circuit is shown below
It the state Q_{A}Q_{B} of the counter at the clock time t_{n} is "10" then the state Q_{A}Q_{B} of the counter at t_{n} + 3 (after three clock cycles) will be