The output expression for the Karnaugh map shown below is
The circuit shown below is an example of a
The Boolean expression $\overline{\left(a+\overline b+c+\overline d\right)+\left(b+\overline c\right)}$ simplifies to
Of the four characteristic given below, which are the major requirements for an instrumentation amplifier? P. High common mode rejection ratio Q. High input impedance R. High linearity S. High output impedance
Consider the circuit shown in the figure,. In this circuit R = 1k$\mathrm{\Omega}$, and C=1$\mathrm{\mu}$F. The input voltage is sinusoidal with a frequency of 50 Hz, represented as phasor with magnitude ${V}_{\mathit{i}}$ and phase angle 0 radian as shown in the figure. The output voltage is represented as a phasor with magnitude ${V}_{0}$ and phase angle δ radian. What is the value of the output phase angle δ (in radian) relative to the phase angle of the input voltage?
In the given circuit, the silicon transistor has $\beta =75$and collector voltage ${V}_{c}=9\mathrm{V\; .}$ Then the ratio of ${R}_{B}$ and ${R}_{C}$ is _______.
The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of ${\mathrm{Q}}_{2}{\mathrm{Q}}_{1}{\mathrm{Q}}_{0}=000$. This state ${\mathrm{Q}}_{2}{\mathrm{Q}}_{1}{\mathrm{Q}}_{0}=000$ will repeat after ________ number of cycles of the clock CLK.
f(A,B,C,D) = ΠM (0,1,3,4,5,7,9,11,12,13,14,15) is a maxterm representation of a Boolean function f(A,B,C,D) where A is the MSB and D is the LSB. The equivalent minimized representation of this function is
The op-amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step-voltage ${V}_{i}$= 1 mV is applied at the input at time t = 0 as shown. Assuming that the operational amplifier is not saturated, the time constant (in millisecond) of the output voltage ${V}_{0}$ is
An 8 bit unipolar Successive Approximation Register type ADC is used to convert 3.5 V to digital equal output. The reference voltage is +5 V. The output of ADC at end of 3rd clock pulse after the start of conversion is ________.
The operational amplifier shown in the figure is ideal. The input voltage (in Volt) is ${V}_{1}=2\mathrm{sin}\left(2\mathrm{\pi}\times 2000\mathrm{t}\right)$. The amplitude of the output voltage ${V}_{0}$ (in Volt) is ________.
In the following circuit, the transistor is in active mode and ${V}_{c}$ = 2V. To get ${V}_{c}$= 2V. To get ${V}_{c}$= 4V, we replace ${R}_{c}$ with ${{R}^{\text{'}}}_{c}$ . Then the ratio ${{R}^{\text{'}}}_{c}/{R}_{c}$ is _________.
Consider the following Sum of Products expression,,F. $F=ABC+\overline{A}\overline{B}C+A\overline{)B}C+\overline{A}BC+\overline{A}\overline{B}\overline{C}$ The equivalent Product of Sums expression is
The filters F1 and F2 having characteristics as shown in Figures (a) and (b) are connected as shown in Figure (c).
The cut-off frequencies of F1 and F2 are ${f}_{1}$ and ${f}_{2}$ respectively. If ${f}_{1}$< ${f}_{2}$, the resultant circuit exhibits the characteristics of a
When a bipolar junction transistor is operating in the saturation mode, which one of the following statement is TRUE about the state of its collector-base (CB) and the baseemitter (BE) junctions?
In the following sequential circuit, the initial state (before the first clock pulse ) of the circuit is ${Q}_{1}{Q}_{0}$= 00. The state (${Q}_{1}{Q}_{0}$), immediately after the ${333}^{\mathrm{rd}}$ clock pulse is
A Boolean funcation f(A, B, C, D) = $\mathrm{\Pi}$(1, 5, 12, 15) is to be implemented using an 8$\times $1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs ${S}_{2}{S}_{1}{S}_{0}$ of the multiplexer respectively.
Which one of the following options gives the correct inputs to pins 0,1,2,3,4,5,6,7 in order?
The saturation voltage of the ideal op-amp shown below is ±10 V. The output voltage ${v}_{0}$ of the following circuit in the steady-state is
A cascade of three identical modulo-5 counters has an overall modulus of
In the Wien Bridge oscillator circuit shown in figure, the bridge is balanced when
The magnitude of the mid-band voltage gain of the circuit shown in figure is (assuming ${h}_{fe}$ of the transistor to be 100)
Given that the op-amps in the figure are ideal, the output voltage V_{0} is
Which of the following logic circuits is a realization of the function F whose Karnaugh map is shown in figure
In the figure shown, assume the op-amp to be ideal. Which of the alternatives gives the correct Bode plots for the transfer function $\frac{{V}_{0}\left(\omega \right)}{{V}_{i}\left(\omega \right)}$ ?
An output device is interfaced with 8-bit microprocessor 8085A. The interfacing circuit is shown in figure
The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enable lines ${\mathrm{E}}_{1}$ , ${\overline{\mathrm{E}}}_{2}$ , ${\overline{\mathrm{E}}}_{3}$ . The address of the device is
Which of the following is an invalid state in an 8-4-2-1 Binary Coded Decimal counter
The transistor in the given circuit should always be in active region. Take V_{CE(sat)} =0.2 V, V_{BE} =0.7 V. The maximum value of R_{C} in Ω which can be used, is ______________.
The sinusoidal ac source in the figure has an rms value of $\frac{20}{\sqrt{2}}$ V. Considering all possible values of R_{L}, the minimum value of R_{S} in Ω to avoid burnout of the Zener diode is _________.
Assuming the diodes to be ideal in the figure, for the output to be clipped, the input voltage v_{i} must be outside the range
A 10 kHz even-symmetric square wave is passed through a bandpass filter with centre frequency at 30 kHz and 3 dB passband of 6 kHz. The filter output is
An oscillator circuit using ideal op-amp and diodes is shown in the figure.
The time duration for +ve part of the cycle is $\Delta {t}_{1}$ and for –ve part is $\Delta {t}_{2}$. The value of $\frac{\Delta {t}_{1}-\Delta {t}_{2}}{RC}$ will be _____________.
The SOP (sum of products) form of a Boolean function is $\sum \left(0,1,3,7,11\right),$, where inputs are A,B,C,D (A is MSB, and D is LSB). The equivalent minimized expression of the function is
A JK flip flop can be implemented by T flip-flops. Identify the correct implementation.
In an 8085 microprocessor, the following program is executed
Address location – Instruction
At the end of program, register A contains
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don’t care condition, and Q is the output representing the state.
The logic gate represented by the state diagram is
An operational-amplifier circuit is shown in the figure.
The output of the circuit for a given input v_{i} is
In 8085A microprocessor, the operation performed by the instruction LHLD 2100H is
Two monoshot multivibrators, one positive edge triggered (M_{1}) and another negative edge triggered (M_{2}), are connected as shown in figure
The monoshots M_{1} and M_{2} when triggered produce pulses of width T_{1} and T_{2} respectively, where T_{1}>T_{2}. The steady state output voltage v_{o} of the circuit is
The transfer characteristic of the Op-amp circuit shown in figure is
A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is 000_{2}. The output is pulled high. The output of the circuit follows the sequence
A hysteresis type TTL inverter is used to realize an oscillator in the circuit shown in the figure.
If the lower and upper trigger level voltages are 0.9 V and 1.7 V, the period (in ms), for which output is LOW, is __________.
In the circuit shown below what is the output voltage (V_{out}) in Volts if a silicon transistor Q and an ideal op-amp are used?
In the feedback network shown below, if the feedback factor k is increased, then the
In the circuit shown below, the knee current of the ideal Zener diode is 10 mA. To maintain 5 V across R_{L}, the minimum value of R_{L} in $\Omega $ and the minimum power rating of the Zener diode in mW respectively are
A voltage $1000\mathrm{sin}\omega t$ Volts is applied across YZ. Assuming ideal diodes, the voltage measured across WX in Volts is
The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is ‘0’, then the frequency of the output waveform Q in kHz is
In the circuit shown below, Q_{1} has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If V_{cc} is +5 V, X and Y are digital signals with 0 V as logic 0 and V_{cc} as logic 1, then the Boolean expression for Z is