# GATE Questions & Answers of Analog and Digital Electronics Electrical Engineering

#### Analog and Digital Electronics 120 Question(s) | Weightage 13 (Marks)

In the logic circuit shown in the figure, $Y$ is given by

The op-amp shown in the figure is ideal. The input impedance $\style{font-family:'Times New Roman'}{\frac{v_{in}}{i_{in}}}$ is given by

Which one of the following statements is true about the digital circuit shown in the figure

Digital input signals $A,B,C$ with $A$ as the MSB and $C$ as the LSB are used to realize the Boolean function $f=m_0+m_2+m_3+m_5+m_7$ where $m_i$ denotes the $i^{th}$ minterm. In addition, $F$ has a don’t care for $m_1$. The simplified expression for $F$ is given by

In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain $B=100$. The base-emitter voltage drop is a constant, $V_{BE}=0.7V.$ The value of the Thevenin equivalent resistance $R_{Th}$ (in $\Omega$) as shown in the figure is ______ (up to 2 decimal places).

The Boolean expression $AB+A\overline{)C}+BC$ simplifies to

For the circuit shown in the figure below, assume that diodes D1, D2 and D3 are ideal.

The DC components of voltages v1 and v2, respectively are

The approximate transfer characteristic for the circuit shown below with an ideal operational amplifier and diode will be

The output expression for the Karnaugh map shown below is

The logical gate implemented using then circuit shown below where, $V_1$ and $V_2$ are inputs (with $0\;V$ as digital $0$ and $5\;V$ as digital 1) and $V_{OUT}$ is the output, is

The circuit shown in the figure uses matched transistors with a thermal voltage VT = 25 mV. The base currents of the transistors are negligible. The value of the resistance R in $k\;\Omega$ that is required to provide 1 µA bias current for the differential amplifier block shown is ___________ . (Give the answer up to one decimal place.)

For a 3-input logic circuit shown below, the output $Z$ can be expressed as

For the circuit shown in the figure below, it is given that $V_{CE}=\frac{V_{CC}}V$. The transistor has $\beta=29$ and VBE=0.7 V when the B-E junction is forward biased

For this circuit, the value of $\frac{R_B}R$ is

For the circuit shown below, assume that the OPAMP is ideal.

Which one of the following is TRUE?

In the circuit shown in the figure, the diode used is ideal. The input power factor is__________.(Give the answer up to two decimal places.)

For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions QAQBQC=Q’AQ’BQ’C=100.

The minimum number of clock cycles after which the output Z would again become zero is__________

A temperature in the range of −40° C to 55° C is to be measured with a resolution of 0.1° C. The minimum number of ADC bits required to get a matching dynamic range of the temperature sensor is

Consider the following circuit which uses a 2-to-1 multiplexer as shown in the figure below. The Boolean expression for output F in terms of A and B is

A transistor circuit is given below. The Zener diode breakdown voltage is 5.3 V as shown. Take base to emitter voltage drop to be 0.6 V. The value of the current gain β is _________.

The current state QA QB of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is

A 2-bit flash Analog to Digital Converter (ADC) is given below. The input is 0 ≤ VIN ≤ 3 Volts.The expression for the LSB of the output B0 as a Boolean function of X2, X1, and X0 is

The output expression for the Karnaugh map shown below is

The circuit shown below is an example of a

The Boolean expression $\overline{\left(a+\overline b+c+\overline d\right)+\left(b+\overline c\right)}$ simplifies to

For the circuit shown below, taking the opamp as ideal, the output voltage Vout in terms of the input voltages V1 , V2 and V3 is

Of the four characteristic given below, which are the major requirements for an instrumentation amplifier?
P. High common mode rejection ratio
Q. High input impedance
R. High linearity
S. High output impedance

Consider the circuit shown in the figure,. In this circuit R = 1 k$\mathrm{\Omega }$, and C=1 $\mathrm{\mu }$F. The input voltage is sinusoidal with a frequency of 50 Hz, represented as phasor with magnitude ${V}_{\mathit{i}}$ and phase angle 0 radian as shown in the figure. The output voltage is represented as a phasor with magnitude ${V}_{0}$ and phase angle δ radian. What is the value of the output phase angle δ (in radian) relative to the phase angle of the input voltage?

In the given circuit, the silicon transistor has and $a$ collector voltage Then the ratio of ${R}_{B}$ and ${R}_{C}$ is _______.

In the $4\times1$ multiplexer, the output F is given by $\mathrm F=\mathrm A\oplus\mathrm B\;.$ Find the required input '

The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of ${\mathrm{Q}}_{2}{\mathrm{Q}}_{1}{\mathrm{Q}}_{0}=000$. This state ${\mathrm{Q}}_{2}{\mathrm{Q}}_{1}{\mathrm{Q}}_{0}=000$ will repeat after ________ number of cycles of the clock CLK.

is a maxterm representation of a Boolean function $f\left(A,\;,B,\;C,\;D\right)$ where $A$ is the MSB and $D$ is the LSB. The equivalent minimized representation of this function is

The op-amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step-voltage ${V}_{i}$= 1 mV is applied at the input at time t = 0 as shown. Assuming that the operational amplifier is not saturated, the time constant (in millisecond) of the output voltage ${V}_{0}$ is

An 8 bit unipolar Successive Approximation Register type ADC is used to convert 3.5 V to digital equivalent output. The reference voltage is +5 V. The output of ADC at end of 3rd clock pulse after the start of conversion is ________.

The operational amplifier shown in the figure is ideal. The input voltage (in Volt) is . The amplitude of the output voltage ${V}_{0}$ (in Volt) is ________.

In the following circuit, the transistor is in active mode and $V_C=2\;V$. To get $V_C=4\;V$, we replace ${R}_{c}$ with $R'_C$ . Then the ratio $R'_C/R_C$ is _________.

Consider the following Sum of Products expression,,F.

$F=ABC+\overline{A}\overline{B}C+A\overline{)B}C+\overline{A}BC+\overline{A}\overline{B}\overline{C}$

The equivalent Product of Sums expression is

The filters F1 and F2 having characteristics as shown in Figures (a) and (b) are connected as shown in Figure (c).

The cut-off frequencies of F1 and F2 are ${f}_{1}$ and ${f}_{2}$ respectively. If ${f}_{1}$< ${f}_{2}$, the resultant circuit exhibits the characteristics of a

When a bipolar junction transistor is operating in the saturation mode, which one of the following statement is TRUE about the state of its collector-base (CB) and the baseemitter (BE) junctions?

In the following sequential circuit, the initial state (before the first clock pulse ) of the circuit is ${Q}_{1}{Q}_{0}$= 00. The state (${Q}_{1}{Q}_{0}$), immediately after the ${333}^{\mathrm{rd}}$ clock pulse is

A Boolean funcation $f\left(A,\;B,\;C,\;D\right)=$ $\mathrm{\Pi }$(1, 5, 12, 15) is to be implemented using an 8$×$1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs ${S}_{2}{S}_{1}{S}_{0}$ of the multiplexer respectively.

Which one of the following options gives the correct inputs to pins 0,1,2,3,4,5,6,7 in order?

The saturation voltage of the ideal op-amp shown below is ±10 V. The output voltage ${v}_{0}$ of the following circuit in the steady-state is

A cascade of three identical modulo-5 counters has an overall modulus of

In the Wien Bridge oscillator circuit shown in figure, the bridge is balanced when

The magnitude of the mid-band voltage gain of the circuit shown in figure is (assuming ${h}_{fe}$ of the transistor to be 100)

Given that the op-amps in the figure are ideal, the output voltage V0 is

Which of the following logic circuits is a realization of the function F whose Karnaugh map is shown in figure

In the figure shown, assume the op-amp to be ideal. Which of the alternatives gives the correct Bode plots for the transfer function $\frac{{V}_{0}\left(\omega \right)}{{V}_{i}\left(\omega \right)}$ ?

An output device is interfaced with 8-bit microprocessor 8085A. The interfacing circuit is shown in figure

The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enable lines ${\mathrm{E}}_{1}$ , ${\overline{\mathrm{E}}}_{2}$ , ${\overline{\mathrm{E}}}_{3}$ . The address of the device is

Which of the following is an invalid state in an 8-4-2-1 Binary Coded Decimal counter

The sinusoidal ac source in the figure has an rms value of $\frac{20}{\sqrt{2}}$  V. Considering all possible values of RL, the minimum value of RS in Ω to avoid burnout of the Zener diode is _________.