GATE Questions & Answers of Integrated Circuits Fabrication Process: Oxidation, Diffusion, Ion Implantation, Photolithography, Twin-Tub CMOS Process

What is the Weightage of Integrated Circuits Fabrication Process: Oxidation, Diffusion, Ion Implantation, Photolithography, Twin-Tub CMOS Process in GATE Exam?

Total 2 Questions have been asked from Integrated Circuits Fabrication Process: Oxidation, Diffusion, Ion Implantation, Photolithography, Twin-Tub CMOS Process topic of Electronic Devices subject in previous GATE papers. Average marks 1.50.

In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapor) produces

In the three dimensional view of a silicon n-channel MOS transistor shown below, δ= 20 nm. The transistor is of width 1 μm. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and SiO2, respectively, are 11.7 and 3.9, and ε0 = 8.9 × 10-12 F/m.

The gate-source overlap capacitance is approximately