GATE Questions & Answers of Sequential Circuits: Latches and Flip-Flops, Counters, Shift-Registers and Finite State Machines

What is the Weightage of Sequential Circuits: Latches and Flip-Flops, Counters, Shift-Registers and Finite State Machines in GATE Exam?

Total 24 Questions have been asked from Sequential Circuits: Latches and Flip-Flops, Counters, Shift-Registers and Finite State Machines topic of Digital circuits subject in previous GATE papers. Average marks 1.71.

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R=10 kΩ and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor R is ________

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X,Y and Z, is shown in the figure.

Which one of the following statements is correct?

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is ______.

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ( Rd input). The counter corresponding to this circuit is

A three bit pseudo random number generator is shown. Initially the value of output Y = Y2Y1Y0 is set to 111. The value of output Y after three clock cycles is

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

 Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is __________ .

The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate.

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4.

The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is

The circuit shown in the figure is a

Consider the given circuit.

In this circuit, the race around

When the output Y in the circuit below is "1", it implies that data has

The output of a 3-stage Johnson (twisted ring) counter is fed to a digital-to-analog (D/A) converter as shown in the figure below. Assume all the states of the counter to be unset initially. The waveform which represents the D/A converter output Vo is

Two D flip-flops are connected as a synchronous counter that goes through the following QBQA sequence 0011011000...

The combination to the inputs DA and DB are

Assuming that flip-flops are in reset condition initially, the count sequence observed at QA in the circuit shown is

Refer to the NAND and NOR latches shown in the figure. The inputs (P1,P2) for both the latches are first made (0,1) and then, after a few seconds, made (1,1). The corresponding stable outputs (Q1,Q2) are

What are the counting stages (Q1,Q2) for the counter shown in the figure below?

For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is ΔT.

Which of the following waveforms correctly represents the output at Q1?

For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible

Which of the following statements is true?

The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below:

X = 0, Y = 1;  X = 0, Y = 0;  X =1, Y =1.

The corresponding stable P, Q outputs will be

For the circuit shown, the counter state (Q1Q0) follows the sequence