# GATE Questions & Answers of Logic Gates and their Static CMOS Implementations

## What is the Weightage of Logic Gates and their Static CMOS Implementations in GATE Exam?

Total 9 Questions have been asked from Logic Gates and their Static CMOS Implementations topic of Digital circuits subject in previous GATE papers. Average marks 1.22.

Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

The logic functionality realized by the circuit shown below is

The output F in the digital logic circuit shown in the figure is

In the circuit shown in the figure, if C=0, the expression for Y is

A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles

The output Y in the circuit below is always "1" when

Match the logic gates in Column A with their equivalents in Column B.