# GATE Questions & Answers of 8-bit Microprocessor (8085): Architecture, Programming, Memory and I/O Interfacing

## What is the Weightage of 8-bit Microprocessor (8085): Architecture, Programming, Memory and I/O Interfacing in GATE Exam?

Total 19 Questions have been asked from 8-bit Microprocessor (8085): Architecture, Programming, Memory and I/O Interfacing topic of Digital circuits subject in previous GATE papers. Average marks 1.63.

The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 µs, then the number of T-states needed for executing the instruction is

He following FIVE instructions were executed on an 8085 microprocessor.

MVI A, 33H

MVI B, 78H

CMA

ANI 32H

The Accumulator value immediately after the execution of the fifth instruction is

In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?

An 8 Kbyte ROM with an active low Chip Select input $\left(\overline{)\mathrm{CS}}\right)$ is to be used in an 8085 microprocessor based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as A15 to A0, where A15 is the most significant address bit. Which one of the following logic expressions will generate the correct $\overline{)CS}$ signal for this ROM?

In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in hex) and 0, respectively. If the instruction RLC is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be

In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively.

In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?

Which one of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C?

For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an external device is shown in the figure. The instruction for correct data transfer is

An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the contents of the Accumulator to the 16-bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins A15−A8 is

For 8085 microprocessor, the following program is executed.
MVI A, 05H;
MVI B, 05H;
DCR B;
JNZ PTR;
HLT;

At the end of program, accumulator contains

There are four chips each of 1024 bytes connected to a 16 bit address bus as shown in the figure below. RAMs 1, 2, 3 and 4 respectively are mapped to addresses

An 8085 assembly language program is given below. Assume that the carry flag is initially unset. The content of the accumulator after the execution of the program is

 MVI A, 07H RLC MOV B, A RLC RLC ADD B RRC

In the circuit shown, the device connected to Y5 can have address in the range

For the 8085 assembly language program given below, the content of the accumulator after the execution of the program is

 3000 MVI A, 45H 3002 MOV B, A 3003 STC 3004 CMC 3005 RAR 3006 XRA B

An 8085 executes the following instructions
2710 LXI H, 30A0H
2714 PCHL
All addresses and constants are in Hex. Let PC be the contents of the program counter and HL be the contents of the HL register pair just after executing PCHL.
Which of the following statements is correct

An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped I/O as shown in the figure. The address lines A0 and A1 of the 8085 are used by the 8255 chip to decode internally its three ports and the Control register. The address line A3 to A7 as well as the $IO/\overline{M}$ signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is

An 8085 assembly language program is given below:

 Line 1: MVI A, B5H 2: MVI B, 0EH 3: XRI 69H 4: ADD B 5: ANI 9BH 6: CPI 9FH 7: STA 3010H 8: HLT

The contents of the accumulator just after execution of ADD instruction in line 4 will be