GATE Questions & Answers of Digital circuits Electronics and Communication Engg

The output of the combinational circuit given below is


Identify the circuit below.


The functionality implemented by the circuit below is


In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?

Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?


Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R=10 kΩ and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor R is ________

A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cin is the input carry and Cout is the output carry. A and B are to be used as the select bits with A being the more significant select bit.
Which one of the following statements correctly describes the choice of signals to be connected to the inputs I0, I1, I2 and I3 so that the output is Cout?

An 8 Kbyte ROM with an active low Chip Select input CS is to be used in an 8085 microprocessor based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as A15 to A0, where A15 is the most significant address bit. Which one of the following logic expressions will generate the correct CS signal for this ROM?

In an N bit flash ADC, the analog voltage is fed simultaneously to 2N−1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source Vin (whose output is being converted to digital format) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full scale input change for proper conversion. Assume that the time taken by the thermometer to binary encoder is negligible.
If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate ?

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X,Y and Z, is shown in the figure.

Which one of the following statements is correct?

In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in hex) and 0, respectively. If the instruction RLC is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be

The logic functionality realized by the circuit shown below is


The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

Following is the K-map of a Boolean function of five variables P, Q, R, S and X. The minimum sum-of-product (SOP) expression for the function is


For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns,1.5 ns and 1 ns, respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is __________


For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively.

A 16kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to number of columns). The minimum number of address lines needed for the row decoder is ______.

Consider a four bit D to A converter. The analog value corresponding to digital signals of values 0000 and 0001 are 0 V and 0.0625 V respectively. The analog value (in Volts) corresponding to the digital signal 1111 is ________.

The Boolean expression $ \begin{array}{l}F(X,Y,Z)=(\overline XY\overline Z)+X\overline Y\overline Z+XY\overline Z+XYZ\\\end{array} $. converted into the canonical product of sum (POS) form is

A 3-input majority gate is defined by the logic function $ M(a,b,c)=ab+bc+ca $. Which one of the following gates is represented by the function MMa,b,c,Ma,b,c,c?

In the figure shown, the output Y is required to be Y=A B+C D. The gates G1 and G2 must be, respectively,


In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?

A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is ______.

A function of Boolean variables X, Y and Z is expressed in terms of the min-terms as

F(X,Y,Z) = (1, 2, 5, 6, 7)

Which one of the product of sums given below is equal to the function F(X, Y, Z)?

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

A 1-to-8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB) and Y0 to Y7 as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input E and address inputs A0 and A1) as shown in the figure. Din, S0, S1 and S2 are to be connected to P,Q,R and S , but not necessarily in this order. The respective input connections to P,Q,R and S terminals should be

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ( Rd input). The counter corresponding to this circuit is

Which one of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C?

A three bit pseudo random number generator is shown. Initially the value of output Y = Y2Y1Y0 is set to 111. The value of output Y after three clock cycles is

A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown.

Which one of the following statements is TRUE?

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

The Boolean expression X+YX+Y+XY¯+X¯¯ simplifies to

 Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is __________ .

The output F in the digital logic circuit shown in the figure is

Consider the Boolean function, F=w,x,y,z=wy+xy+w¯xyz+w¯ x¯y+xz+x¯y¯z¯   Which one of the following is the complete set of essential prime implicants?

The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate.

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

For an n-variable Boolean function, the maximum number of prime implicants is

The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) form is __________ .

In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by

In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4.

The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is

For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an external device is shown in the figure. The instruction for correct data transfer is

The circuit shown in the figure is a

Consider the multiplexer based logic circuit shown in the figure.

Which one of the following Boolean functions is realized by the circuit?

If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in

In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by

If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor?

In the circuit shown in the figure, if C=0, the expression for Y is

The output (Y) of the circuit shown in the figure is

An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by

A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________.

An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the contents of the Accumulator to the 16-bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins A15−A8 is

A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles

For 8085 microprocessor, the following program is executed.
          MVI A, 05H;
          MVI B, 05H;
          DCR B;
          JNZ PTR;
          ADI 03H;

At the end of program, accumulator contains

In the circuit shown below, Q1 has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If Vcc is +5 V, X and Y are digital signals with 0 V as logic 0 and Vcc as logic 1, then the Boolean expression for Z is

There are four chips each of 1024 bytes connected to a 16 bit address bus as shown in the figure below. RAMs 1, 2, 3 and 4 respectively are mapped to addresses

Consider the given circuit.

In this circuit, the race around

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

In the circuit shown

In the sum of products function f(X,Y,Z)=2,3,4,5,the prime implicants are

When the output Y in the circuit below is "1", it implies that data has

The logic function implemented by the circuit below is (ground implies a logic "0")

The output Y in the circuit below is always "1" when

An 8085 assembly language program is given below. Assume that the carry flag is initially unset. The content of the accumulator after the execution of the program is

MVI A, 07H

The output of a 3-stage Johnson (twisted ring) counter is fed to a digital-to-analog (D/A) converter as shown in the figure below. Assume all the states of the counter to be unset initially. The waveform which represents the D/A converter output Vo is

Two D flip-flops are connected as a synchronous counter that goes through the following QBQA sequence 0011011000...

The combination to the inputs DA and DB are

Match the logic gates in Column A with their equivalents in Column B.

For the output F to be 1 in the logic circuit shown, the input combination should be

In the circuit shown, the device connected to Y5 can have address in the range

Assuming that flip-flops are in reset condition initially, the count sequence observed at QA in the circuit shown is

The Boolean function realized by the logic circuit shown is

For the 8085 assembly language program given below, the content of the accumulator after the execution of the program is

3000 MVI A, 45H
3002 MOV B, A
3003 STC    
3004 CMC    
3005 RAR    
3006 XRA B  

In a microprocessor, the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set, but the interrupt can be delayed or rejected. Such an interrupt is