Identify the circuit below.
The functionality implemented by the circuit below is
The average power dissipated (in mW) in the resistor R is ________
Which one of the following statements is correct?
The logic functionality realized by the circuit shown below is
The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is
If the clock (Clk) frequency is 1 GHz, then the counter behaves as a
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively.
A 16kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to number of columns). The minimum number of address lines needed for the row decoder is ______.
Consider a four bit D to A converter. The analog value corresponding to digital signals of values 0000 and 0001 are 0 V and 0.0625 V respectively. The analog value (in Volts) corresponding to the digital signal 1111 is ________.
The Boolean expression $\mathrm{F}\left(\mathrm{X},\mathrm{Y},\mathrm{Z}\right)=\overline{\mathrm{X}}\mathrm{Y}\overline{\mathrm{Z}}+\mathrm{X}\overline{\mathrm{Y}}\overline{\mathrm{Z}}+\mathrm{XY}\overline{\mathrm{Z}}+\mathrm{XYZ}$. converted into the canonical product of sum (POS) form is
A 3-input majority gate is defined by the logic function M(a,b,c) = ab+bc+ca. Which one of the following gates is represented by the function $M\left(\overline{)M\left(a,b,c\right)},M\left(a,b,\overline{)c}\right),c\right)$?
In the figure shown, the output Y is required to be $Y=AB+\overline{)C}\overline{)D}$ . The gates G1 and G2 must be, respectively,
In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?
A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is ______.
A function of Boolean variables X, Y and Z is expressed in terms of the min-terms as
F(X,Y,Z) = $\sum $(1, 2, 5, 6, 7)
Which one of the product of sums given below is equal to the function F(X, Y, Z)?
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a
A 1-to-8 demultiplexer with data input D_{in}, address inputs S_{0}, S_{1}, S_{2} (with S_{0} as the LSB) and ${\overline{)\mathrm{Y}}}_{0}\mathrm{to}{\overline{)\mathrm{Y}}}_{7}$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $\overline{)\mathrm{E}}$ and address inputs A_{0} and A_{1}) as shown in the figure. D_{in}, S_{0}, S_{1} and S_{2} are to be connected to P,Q,R and S , but not necessarily in this order. The respective input connections to P,Q,R and S terminals should be
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ( $\overline{){R}_{d}}$ input). The counter corresponding to this circuit is
Which one of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C?
A three bit pseudo random number generator is shown. Initially the value of output Y = Y_{2}Y_{1}Y_{0} is set to 111. The value of output Y after three clock cycles is
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown.
Which one of the following statements is TRUE?
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing
The Boolean expression $\left(\mathrm{X}+\mathrm{Y}\right)\left(\mathrm{X}+\overline{)\mathrm{Y}}\right)+\overline{\left(\mathrm{X}\overline{\mathrm{Y}}\right)+\overline{\mathrm{X}}}$ simplifies to
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is __________ .
The output F in the digital logic circuit shown in the figure is
Consider the Boolean function, $F=\left(w,x,y,z\right)=wy+xy+\overline{w}xyz+\overline{w}\overline{x}y+xz+\overline{x}\overline{y}\overline{z}$ Which one of the following is the complete set of essential prime implicants?
The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate.
Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?
For an n-variable Boolean function, the maximum number of prime implicants is
The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) form is __________ .
In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4.
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is
For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI_{0} – DI_{7}) from an external device is shown in the figure. The instruction for correct data transfer is
The circuit shown in the figure is a
Consider the multiplexer based logic circuit shown in the figure.
Which one of the following Boolean functions is realized by the circuit?
If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in
In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by
If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor?
In the circuit shown in the figure, if C=0, the expression for Y is
The output (Y) of the circuit shown in the figure is
An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________.
An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the contents of the Accumulator to the 16-bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins A_{15}−A_{8} is
A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles
For 8085 microprocessor, the following program is executed. MVI A, 05H; MVI B, 05H; PTR: ADD B; DCR B; JNZ PTR; ADI 03H; HLT; At the end of program, accumulator contains
In the circuit shown below, Q_{1} has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If V_{cc} is +5 V, X and Y are digital signals with 0 V as logic 0 and V_{cc} as logic 1, then the Boolean expression for Z is
There are four chips each of 1024 bytes connected to a 16 bit address bus as shown in the figure below. RAMs 1, 2, 3 and 4 respectively are mapped to addresses
Consider the given circuit.
In this circuit, the race around
The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is
In the circuit shown
In the sum of products function f(X,Y,Z)=$\sum \left(2,3,4,5\right)$,the prime implicants are
When the output Y in the circuit below is "1", it implies that data has
The logic function implemented by the circuit below is (ground implies a logic "0")
The output Y in the circuit below is always "1" when
An 8085 assembly language program is given below. Assume that the carry flag is initially unset. The content of the accumulator after the execution of the program is
The output of a 3-stage Johnson (twisted ring) counter is fed to a digital-to-analog (D/A) converter as shown in the figure below. Assume all the states of the counter to be unset initially. The waveform which represents the D/A converter output V_{o} is
Two D flip-flops are connected as a synchronous counter that goes through the following Q_{B}Q_{A} sequence $\phantom{\rule{0ex}{0ex}}00\to 11\to 01\to 10\to 00\to ...$
The combination to the inputs D_{A} and D_{B} are
Match the logic gates in Column A with their equivalents in Column B.
For the output F to be 1 in the logic circuit shown, the input combination should be
In the circuit shown, the device connected to Y5 can have address in the range
Assuming that flip-flops are in reset condition initially, the count sequence observed at Q_{A} in the circuit shown is