# GATE Questions & Answers of Digital circuits Electronics and Communication Engg

#### Digital circuits 120 Question(s) | Weightage 12 (Marks)

The logic function $\begin{array}{l}f\left(X,\;Y\right)\\\end{array}$ realized by the given circuit is

A function $F\left(A,\;B,\;C\right)$ defined by three Boolean variables $A$, $B$ and $C$ when expressed as sum of products is given by

$F=\overline A\cdot\overline B\cdot\overline C\;+\;\overline A\cdot B\cdot\overline C\;+\;A+\overline B+\overline C$

where, $\begin{array}{l}\overline A,\;\overline B\\\end{array}$, and $\begin{array}{l}\overline C\\\end{array}$ are the complements of the respective variables. The product of sums (POS) form of the function F is

A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is _______.

A four-variable Boolean function is realized using $4\times1$ multiplexers as shown in the figure.

The minimized expression for $F\left(U,\;V,\;W,\;X\right)$ is

A $2\times2$ ROM array is built with the help of diodes as shown in the circuit below. Here W0 and W1 are signals that select the word lines and B0 and B1 are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation.

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to $D_{ij}$ (where $i$ = 0 or 1 and $j$ = 0 or 1) stored in the ROM?

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $\bigtriangleup T/T_{CK}$ = 0.15, where the parameters $\bigtriangleup T$ and $\bigtriangleup T_{CK}$ are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

If the probability of input data bit $\left(D_{in}\right)$ transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _______.

The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.

The number of distinct values of $X_3X_2X_1X_0$ (out of the 16 possible values) that give $Y=1$ is _______.

In the latch circuit shown, the NAND gates have non-zero, but unequal proportion delays. The present input condition is: P=Q=’0’. If the input condition is changed simultaneously to P=Q=’1’, the outputs X and Y are

The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 µs, then the number of T-states needed for executing the instruction is

Consider the D-Latch shows in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty at the output at the latch in percentage is__________

Which one of the following gives the simplified sum of products expression for the Boolean function $F={m}_{0}+{m}_{2}+{m}_{3}+{m}_{5}$ , where $m_0,\;m_2,\;m_3$ and $m_5$ are minterms corresponding to the inputs A,B and C with A as the MSB and C as the LSB?

A 4-bit shift register circuit configured for right-shift operation, i.e. DinA, AB, BC, CD, is shown. If the present state of the shift register is ABCD =1101, the number of clock cycles required to reach the state ABCD =1111 is_________.

He following FIVE instructions were executed on an 8085 microprocessor.

MVI A, 33H

MVI B, 78H

CMA

ANI 32H

The Accumulator value immediately after the execution of the fifth instruction is

A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are QAQB=00, 01, 10, and 11.

Assume that XIN is held at a constant logic level throughout the operation of the FSM. When the FSM initialized to the state QAQB=00 and clocked, after a few clock cycle, it starts cycling through

For the circuit shown in the figure , P and Q are the inputs and Y is the output.

The logic implemented by the circuit is

Consider the circuit shown in the figure.

The Boolean expression F implemented by the circuit is

In a DRAM,

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input ‘In’ and an output ‘Out’. The initial state of the FSM is S0.

If the input sequence is 10101101001101, staring with the left-most bit, then the number of items ‘Out’ will be 1 is_____________

Figure I shows a 4-bit ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder are initially reset to 0.

At t = 0, the input to the 4-bit adder are changed to XXXX= 1100, YYYY= 0100 and Z= 1. The output of the ripple carry adder will be stable at t (in ns)=____________

A programmable logic array (PLA) is shown in the figure.

The Boolean function F implements is

The output of the combinational circuit given below is

Identify the circuit below.

The functionality implemented by the circuit below is

In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?

Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R=10 kΩ and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor R is ________

A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cin is the input carry and Cout is the output carry. A and B are to be used as the select bits with A being the more significant select bit.
Which one of the following statements correctly describes the choice of signals to be connected to the inputs I0, I1, I2 and I3 so that the output is Cout?

An 8 Kbyte ROM with an active low Chip Select input $\left(\overline{)\mathrm{CS}}\right)$ is to be used in an 8085 microprocessor based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as A15 to A0, where A15 is the most significant address bit. Which one of the following logic expressions will generate the correct $\overline{)CS}$ signal for this ROM?

In an N bit flash ADC, the analog voltage is fed simultaneously to 2N−1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source Vin (whose output is being converted to digital format) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full scale input change for proper conversion. Assume that the time taken by the thermometer to binary encoder is negligible.
If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate ?

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X,Y and Z, is shown in the figure.

Which one of the following statements is correct?

In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in hex) and 0, respectively. If the instruction RLC is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be

The logic functionality realized by the circuit shown below is

The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

Following is the K-map of a Boolean function of five variables P, Q, R, S and X. The minimum sum-of-product (SOP) expression for the function is

For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns,1.5 ns and 1 ns, respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is __________

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively.

A 16kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to number of columns). The minimum number of address lines needed for the row decoder is ______.

Consider a four bit D to A converter. The analog value corresponding to digital signals of values 0000 and 0001 are 0 V and 0.0625 V respectively. The analog value (in Volts) corresponding to the digital signal 1111 is ________.

The Boolean expression $\begin{array}{l}F(X,Y,Z)=(\overline XY\overline Z)+X\overline Y\overline Z+XY\overline Z+XYZ\\\end{array}$. converted into the canonical product of sum (POS) form is

A 3-input majority gate is defined by the logic function $M(a,b,c)=ab+bc+ca$. Which one of the following gates is represented by the function $M\left(\overline{)M\left(a,b,c\right)},M\left(a,b,\overline{)c}\right),c\right)$?

In the figure shown, the output Y is required to be . The gates G1 and G2 must be, respectively,

In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?

A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is ______.

A function of Boolean variables X, Y and Z is expressed in terms of the min-terms as

F(X,Y,Z) = $\sum$(1, 2, 5, 6, 7)

Which one of the product of sums given below is equal to the function F(X, Y, Z)?

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

A 1-to-8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB) and as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $\overline{)\mathrm{E}}$ and address inputs A0 and A1) as shown in the figure. Din, S0, S1 and S2 are to be connected to P,Q,R and S , but not necessarily in this order. The respective input connections to P,Q,R and S terminals should be

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ( $\overline{){R}_{d}}$ input). The counter corresponding to this circuit is

Which one of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C?

A three bit pseudo random number generator is shown. Initially the value of output Y = Y2Y1Y0 is set to 111. The value of output Y after three clock cycles is

A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown.

Which one of the following statements is TRUE?

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

The Boolean expression $\left(\mathrm{X}+\mathrm{Y}\right)\left(\mathrm{X}+\overline{)\mathrm{Y}}\right)+\overline{\left(\mathrm{X}\overline{\mathrm{Y}}\right)+\overline{\mathrm{X}}}$ simplifies to

Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is __________ .

The output F in the digital logic circuit shown in the figure is

Consider the Boolean function, Which one of the following is the complete set of essential prime implicants?

The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate.

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

For an n-variable Boolean function, the maximum number of prime implicants is

The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) form is __________ .

In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by

In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4.

The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is

For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an external device is shown in the figure. The instruction for correct data transfer is

The circuit shown in the figure is a

Consider the multiplexer based logic circuit shown in the figure.

Which one of the following Boolean functions is realized by the circuit?

If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in

In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by

If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor?