# Electronics and Communication Engg - GATE 2017 Paper Solution

Consider the 5 x 5 matrix

$A=\left[\begin{array}{ccccc}1& 2& 3& 4& 5\\ 5& 1& 2& 3& 4\\ 4& 5& 1& 2& 3\\ 3& 4& 5& 1& 2\\ 2& 3& 4& 5& 1\end{array}\right]$

It is given that A has only one real eigenvalue. Then the real eigenvalue of A is

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The rank of the matrix $M=\left[\begin{array}{ccc}5& 10& 10\\ 1& 0& 2\\ 3& 6& 6\end{array}\right]$ is

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Consider the following statement about the linear dependence of the real valued function $y_1=1,y_2=x$ and $y_3=x^2$, over the field of real of real numbers.

I.           $y_1,\;y_2$ and $y_3$ are linearly independent on $-1\le x\le 0$

II.          $y_1,\;y_2$ and $y_3$ are linearly dependent on $0\leq x\leq1$

III.         $y_1,\;y_2$ and $y_3$ are linearly independent on $0\le x\le 1$

IV.         $y_1,\;y_2$ and $y_3$ and  are linearly dependent on $-1\le x\le 0$

Which one among the following is correct?

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Three fair cubical dice are thrown simultaneously. The probably that all three dice have the same number of dots on the faces showing us is (up to third decimal place) ____________.

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Consider the following statements for continuous-time linear time invariant (LTI) system.

I.       There is no bounded input bounded output (BIBO) stable system with a pole in the right half of the complex plane.

II.       There is no casual and BIBO stable system with a pole in the right half of the complex plane.

Which one among the following is correct?

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Consider a single input single output discrete-time system with $x\left[n\right]$ as input and $y\left[n\right]$ as output, where the two are related as

$y\left[n\right]=\left\{\begin{array}{l}\;\;\;\;\;\;\;\;\;\;\;\;n\left|x\left[n\right]\right|,\;\;\;\;\;\;\mathrm{for}\;0\leq\mathrm n\leq10\\x\left[n\right]-x\left[n-1\right],\;\;\;\;\;\;\;\mathrm{otherwise}.\end{array}\right.$

Which one of the following statement is true about the system?

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In the circuit shown, the positive angular frequency ω (in radians per second) at which the magnitude of the phase difference between the voltages V1 and V2 equals $\frac{\mathrm{\pi }}{4}$ radians, is_________.

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A periodic signal x(t) has a trigonometric Fourier aeries expansion

$x\left(t\right)=a_0+\sum\limits_{n=1}^\infty\left(a_n\;\cos\omega_0t\;+\;b_n\sin\;n\omega_0t\right)$

If $x\left(t\right)=-x\left(-t\right)=\left(t-\pi/\omega_0\right)$, we can conclude that

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A bar of Gallium Arsenide (GaAs) is doped with Silicon such that the Silicon atoms occupy Gallium and Arsenic sites in the GaAs crystal. Which one of the following statements is true?

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An n+ -n Silicon device is fabricated with uniform and nono-degenerate donor doping concentration of ND1 =1 × 1018 cm-3 and ND2 =1 × 1015 cm-3 corresponding to the n+ and n regions respectively. At the operational temperature T, assume complete impurity ionization, kT/q=25mV, and intrinsic carrier concentration to be ni = 1 × 1010 cm-3. What is the magnitude of the built-in potential of this device?

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For a narrow base PNP BJT, the excess minority carrier concentration ($\triangle n_E$ for emitter,$\triangle p_B$ for base,$\triangle n_C$ for collector) normalized to equilibrium minority carrier concentration ($n_{E0}$ for emitter,$n_{B0}$ for base,$n_{C0}$ for collector) in the quasi-neutral emitter, base and collector regions are shown below. Which one of the following biasing modes is the transistor operating in?

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For the operational amplifier circuit shown, the output saturation voltages are ±15V. The upper and lower threshold voltages for the circuit are, respectively,

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A good transconductance amplifier should have

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A Miller effect in the context of a Common Emitter amplifier explains

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In the latch circuit shown, the NAND gates have non-zero, but unequal proportion delays. The present input condition is: P=Q=’0’. If the input condition is changed simultaneously to P=Q=’1’, the outputs X and Y are

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The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 µs, then the number of T-states needed for executing the instruction is

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Consider the D-Latch shows in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty at the output at the latch in percentage is__________

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The open loop transfer function $G\left(s\right)=\frac{\left(s+1\right)}{{s}^{p}\left(s+2\right)\left(s+3\right)}$ where p is an integer, is connected in unity feedback configuration as shown in the figure.

Given that the steady state error is zero for unit and 6 for unit ramp input, the value of the parameter p is_________

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Consider a stable system with transfer function $G\left(s\right)=\frac{{s}^{p}+{b}_{1}{s}^{p-1}+···+{b}_{p}}{{s}^{q}+{a}_{1}{s}^{q-1}+···+{a}_{q}}$ where b1, …, bp and a1, … , aq are real valued constant. The slop of the Bode log magnitude curve of G(s) converges to -60 dB /decade as ω→∞. A possible pair of values for p and q is

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Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?