GATE Papers >> ECE >> 2018 >> Question No 56

Question No. 56 ECE | GATE 2018

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data $ D_{in} $ using clock $CK$. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $ \bigtriangleup T/T_{CK} $ = 0.15, where the parameters $\bigtriangleup T$ and $ \bigtriangleup T_{CK} $ are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

If the probability of input data bit $ \left(D_{in}\right) $ transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _______.


Answer : 0.82 to 0.86


Comments
R6Upl1 http://pills2sale.com/ levitra nizagara

Posted on  18/10/2020 19:39:45  by  dobsonz
kplk7z http://pills2sale.com/ viagra cialis buy

Posted on  01/11/2020 20:52:09  by  johnanx
NUWZ4v https://www.quora.com/What-the-top-SEO-keywords-for-essay-you-know/answer/Alan-Smith-1772 write my essay

Posted on  04/12/2020 01:53:26  by  dobson
YEGRHY http://xnxx.in.net/ xnxx videos

Posted on  12/12/2020 23:46:54  by  johnan
tKQ5QW https://writemyessayforme.web.fc2.com/

Posted on  13/12/2020 04:40:59  by  dobson
9h4E0r https://writemyessayforme.web.fc2.com/#writemyessay

Posted on  15/12/2020 05:40:20  by  dobson
9YRAxf https://writemyessayforme.web.fc2.com/octavio-paz-essay-day-of-the-dead.html

Posted on  09/01/2021 10:02:47  by  dobson
nusZdR http://waldorfdollshop.us/ waldorf doll

Posted on  09/01/2021 14:17:32  by  johnanz
9BeVtP https://beeg.x.fc2.com/

Posted on  26/01/2021 15:03:28  by  markus
31yj4L https://buyzudena.web.fc2.com/

Posted on  27/01/2021 12:25:54  by  markus
Leave a comment
Go