GATE Questions & Answers of Combinational and Sequential Circuits

Consider three 4-variable functions f₁, f₂, and f₃, which are expressed in sum-of-minterms as f₁ = $\sum$ (0, 2, 5, 8, 14),   f₂ = $\sum$ (2, 3, 6, 8, 14, 15),   f₃ = $\sum$ (2, 7, 11, 14) For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:

•  (A)  $\sum$ (7, 8, 11)
•  (B)  $\sum$ (2, 7, 8, 11, 14)
•  (C)  $\sum$ (2, 14)
•  (D)  $\sum$ (0, 2, 3, 5, 6, 7, 8, 11, 14, 15)

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is .

Consider the two cascaded 2-to-1 multiplexers as shown in the figure.

The minimal sum of products form of the output $X$ is

•  (A)  $\style{font-family:'Times New Roman'}{\overline P\;\overline Q\;+\;PQR}$
•  (B)  $\style{font-family:'Times New Roman'}{\overline PQ\;+\;QR}$
•  (C)  $\style{font-family:'Times New Roman'}{P\;Q\;+\;\overline P\;\overline Q\;R}$
•  (D)  $\overline{Q} \overline{R} +PQR$

Consider the 4-to-1 multiplexer with two select lines S₁ and S₀ given below.

The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is

•  (A) $\overline{P}Q+Q\overline{R}+P\overline{Q}R$
•  (B) $\overline{P}Q+\overline{P}Q\overline{R}+PQ\overline{R}+P\overline{Q}R$
•  (C) $\overline{P}QR+\overline{P}Q\overline{R}+Q\overline{R}+P\overline{Q}R$
•  (D) $PQ\overline{R}$

Let k= 2ⁿ. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2ⁿ bit decoder. This circuit is equivalent to a

•  (A) k-bit binary up counter.
•  (B) k-bit binary down counter.
•  (C) k-bit ring counter.
•  (D) k-bit Johnson counter.

The above synchronous sequential circuit built using JK flip flop is initialized with Q₂Q₁Q₀=000.THe state sequence for these circuit for next 3 clock cycle is

•  (A) 001,010,011
•  (B) 111,110,101
•  (C) 100,110,111
•  (D) 100,011,001

In the following truth table, V = 1 if and only if the input is valid.

What function does the truth table represent?

•  (A) Priority encoder
•  (B) Decoder
•  (C) Multiplexer
•  (D) Demultiplexer

The truth table

represents the Boolean function

•  (A) X
•  (B) X + Y
•  (C) X $\oplus$ Y
•  (D) Y

Consider the following circuit involving three D-type flip-flop used ina certain type of  counter configuration.

if at some instance prior to the occurance of the clock edge  P ,Q,and R have value 0, 1 and 0 respectively, what shall be the val ue of PQR after the clock edge?

•  (A) 000
•  (B) 001
•  (C) 010
•  (D) 011

Consider the following circuit involving three D-type flip-flop used ina certain type of  counter configuration.

If all the flip-flop were reset to 0 at power on ,what is the total number of distinct outputs (states) represented by PQR generated by the counter?

•  (A) 3
•  (B) 4
•  (C) 5
•  (D) 6

The Boolean expression for the output f of the multiplexer shown below is

•  (A) $\overline{P\oplus Q\oplus R}$
•  (B) $P\oplus Q\oplus R$
•  (C) $P+Q+R$
•  (D) $\overline{P+Q+R}$

What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?

•  (A) $\overline{Q+R}$
•  (B) $\overline{P+Q}$
•  (C) $\overline{P+R}$
•  (D) $\overline{P+Q+R}$

In the sequential circuit shown below, if the initial value of the output Q₁Q₀ is 00, what are the next four values of Q₁Q₀?

•  (A) 11,10,01,00
•  (B) 10,11,01,00
•  (C) 10,00,01,11
•  (D) 11,10,00,01

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?

•  (A) 7
•  (B) 8
•  (C) 9
•  (D) 10

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

•  (A) 2ⁿ line to 1 line
•  (B) 2ⁿ⁺¹ line to 1 line
•  (C) 2^n-1 line to 1 line
•  (D) 2^n-2 line to 1 line

The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”):

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

•  (A)   0, 3, 4
•  (B)   0, 3, 4, 5
•  (C)   0, 1, 2, 3, 4
•  (D)   0, 1, 2, 3, 4, 5