Questions & Answers of Combinational Circuits

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is .

Consider the two cascaded 2-to-1 multiplexers as shown in the figure.

The minimal sum of products form of the output X is

Consider the 4-to-1 multiplexer with two select lines S1 and S0 given below.

The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is

Let k= 2n. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2n bit decoder. This circuit is equivalent to a

The above synchronous sequential circuit built using JK flip flop is initialized with Q2Q1Q0=000.THe state sequence for these circuit for next 3 clock cycle is

In the following truth table, V = 1 if and only if the input is valid.

Inputs Outputs
D0 D1 D2 D3 X0 X1 V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

What function does the truth table represent?

The truth table

X Y f (X, Y)
0 0 0
0 1 0
1 0 1
1 1 1

represents the Boolean function

Consider the following circuit involving three D-type flip-flop used ina certain type of  counter configuration.

if at some instance prior to the occurance of the clock edge P,Q,and R have value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?

Consider the following circuit involving three D-type flip-flop used ina certain type of  counter configuration.

If all the flip-flop were reset to 0 at power on ,what is the total number of distinct outputs (states) represented by PQR generated by the counter?

The Boolean expression for the output f of the multiplexer shown below is

What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?

In the sequential circuit shown below, if the initial value of the output Q1Q0 is 00, what are the next four values of Q1Q0?

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”):

Clear Clock Load Count Function
1 X X X Clear to 0
0 X 0 0 No change
0 1 X Load input
0 0 1 Count next

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence: