## What is the Weightage of Machine instructions and addressing modes in GATE Exam?

Total 19 Questions have been asked from Machine instructions and addressing modes topic of Computer Organization and Architecture subject in previous GATE papers. Average marks 1.84.

A processor has 16 integer registers (R0, R1, .. , R15) and 64 floating point registers (F0, F1,… , F63). It uses a 2-byte instruction format. There are four categories of instructions:Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is __________.

Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instruction use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence.

 Instr. No. Instruction i   : add R2, R3, R4 i+1 : sub R5, R6, R7 i+2 : cmp R1, R9, R10 i+3 : beq R1, offset
If the target of the branch instruction is i, then the decimal value of the offset is ______

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is __________ .

For computer based on three-address instruction formats, each address feild can be used to specify which of the following:
(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register

Consider the sequence of machine instructions given below.

MUL R5, R0, R1
DIV R6, R2, R3
SUB R8, R7, R4

In the above sequence, R0 to R8 are general purpose registers. In the instruction shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode(IF), (2) Operand Fetch (OF), (3) Perform Operation(PO) and (4) Write back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instuction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is _________.

Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format.
OP Ri, Rj, Rk
Where operation Op is performed on contents of registers Rj and Rk and the result is stored in register Ri.
I2: MUL R7., R1, R3
I3: SUB R4, R1, R5
I5: MUL R7, R8, R9

Consider the following three statements.

S1:There is an anti-dependence between instruction I2 and I5
S2:There is an anti-dependence between instructions I2 and I4
S3:Within an instruction pipeline an anti-dependence always creates one or more stalls

Which one of above statements is/are correct?

In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from

Consider the following sequence of micro-operations.
MBR ← PC
MAR ← X
PC ← Y
Memory ← MBR
Which one of the following is a possible operation performed by this sequence?

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment.
c = a + b;
d = c * a;
e = c + a;
x = c * c;
if (x > a) {
y = a * a;
}
else {
d = d * d;
e = e * e;
}

Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code?

The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment.
c = a + b;
d = c * a;
e = c + a;
x = c * c;
if (x > a) {
y = a * a;
}
else {
d = d * d;
e = e * e;
}

What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.

Consider a hypothetical processor with an instruction of type LW R1 , 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

Consider evaluating the following expression tree on a machine with load-store architecture in which memory can be accessed only through load and store instructions. The variables a, b, c, d and e are initially stored in memory. The binary operators used in this expression tree can be evaluated by the machine only when the operands are in registers. The instructions produce result only in a register. If no intermediate results can be stored in memory, what is the minimum number of registers needed to evaluate this expression?

Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor?
I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction

Delayed branching can help in the handling of control hazards

For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false

Delayed branching can help in the handling of control hazards

The following code is to run on a pipelined processor with one branch delay slot:
I1 : ADD R2 $←$ R7 + R8
I2 : SUB R4 $←$ R5 - R6
I3 : ADD R1 $←$ R2 + R3
I4 : STORE Memory [R4] $←$ R1
BRANCH to Label if R1 == 0
Which of the instructions I1,  I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

 Instruction Operation Instruction size (no. of words) MOV R1, (3000) R1$←$M[3000] 2 LOOP: MOV R2, (R3) R2$←$M[R3] 1 ADD R2, R1 R2$←$R1 + R2 1 MOV (R3), R2 M [R3]$←$R2 1 INC R3 R3$←$R3 + 1 1 DEC R1 R1$←$R1 – 1 1 BNZ LOOP Branch on not zero 2 HALT Stop 1

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

 Instruction Operation Instruction size (no. of words) MOV R1, (3000) R1$←$M[3000] 2 LOOP: MOV R2, (R3) R2$←$M[R3] 1 ADD R2, R1 R2$←$R1 + R2 1 MOV (R3), R2 M [R3]$←$R2 1 INC R3 R3$←$R3 + 1 1 DEC R1 R1$←$R1 – 1 1 BNZ LOOP Branch on not zero 2 HALT Stop 1

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

 Instruction Operation Instruction size (no. of words) MOV R1, (3000) R1$←$M[3000] 2 LOOP: MOV R2, (R3) R2$←$M[R3] 1 ADD R2, R1 R2$←$R1 + R2 1 MOV (R3), R2 M [R3]$←$R2 1 INC R3 R3$←$R3 + 1 1 DEC R1 R1$←$R1 – 1 1 BNZ LOOP Branch on not zero 2 HALT Stop 1