GATE Questions & Answers of ALU, Data-path and Control Unit

What is the Weightage of ALU, Data-path and Control Unit in GATE Exam?

Total 7 Questions have been asked from ALU, Data-path and Control Unit topic of Computer Organization and Architecture subject in previous GATE papers. Average marks 1.57.

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________.

Consider two processors p1 and p2 executing the same instruction set. Assume that under identicalv conditions, for the same input, a program running on p2 takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on p2. If the clock frequency of p1 is 1GHz, then the clock frequency of p2 (in GHz) is _________.

The amount of ROM needed to implement a 4 bit multiplier is

On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.

     Initialize the address register
     Initialize the count to 500
LOOP:Load a byte from device
     Store in memory at address given by address register
     Increment the address register
     Decrement the count
     If count != 0 go to LOOP

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?

A CPU generally handles an interrupt by executing an interrupt service routine

Which of the following is/are true of the auto-increment addressing mode?

I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for

I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches